Written by Stephen Niles
(Reuters) – In the past, chip makers such as Intel Corp and Taiwan Semiconductor Manufacturing Co. have raced with each other to make features on chips smaller and smaller to cram more computing power into a single chip.
But the latest race in chipmaking is stacking “chips” or “tiles” — small squares cut into slices from what would normally be a single larger chip — on top of a silicon substrate in one package, mixing and matching different technologies instead of trying to make a chip big one.
What analysts call 3D packaging saves costs. It can also help manufacturers improve chip performance even as they push the physical limits of how to get microchip features.
Intel on Monday outlined a new 3D packaging technology that analysts said is outperforming its competitors in the field.
Intel believes the technology can help it win more packaging customers like Amazon.com, which it announced on Monday, although parts of the chips used by those customers may still be made by Intel’s competitors.
“We’re not going to package everything on one piece of silicone in the future,” said Kevin Crewell, principal analyst at TIRIAS Research.
What is 3D Foil Packaging?
To make a 3D chip, chip makers cut the chips into “tiles” or “chiplets” that are then stacked on a so-called core die. One of the main benefits is cost control.
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Smaller and faster chip manufacturing technology is always more expensive than slower and larger technology. 3D encapsulation allows chip designers to use “tiles” made with more expensive technology where it matters, such as the brains of a computer chip, and then use outdated technology when speed is less important, saving costs.
What does INTEL technology do?
Several chip makers, including Intel competitor TSMC, have 3D encapsulation technology. What sets Intel packaging apart is that it can take a variety of chips and combine them together without losing performance.
“You can now take very small components from a different manufacturer – internally or externally – and stick them into the packaging much more precisely than you are used to,” said Sanjay Natarajan, co-general manager of logic technology development at Intel.
David Kanter, an analyst at Real World Tech, said another Intel technology is placed on top of the copper pillars, allowing it to absorb electricity more efficiently than other designs — an important advantage for chips inside data centers.
“Imagine you have four little wires or a big piece of copper—that greasy piece of copper would be better,” Kanter said.
Why is packaging important to INTEL’s business?
Earlier this year, Intel announced plans to open chip factories to external customers to compete against TSMC. But winning over customers can take years because designers of complex chips like Advanced Micro Devices Inc or Qualcomm Inc must work closely with manufacturers, and the switch is expensive.
Introducing packaging technologies to these customers allows Intel to get their attention, even if they still want to get important parts of their chips from Intel competitors.
“There is a technical benefit, there is a flexibility benefit and there is a cost benefit,” said Ann B. Kelleher, general manager of technology development at Intel.
(Reporting by Stephen Niles of San Francisco; Editing by David Gregorio)